NVIDIA CUDA 13.5 Brings Vera Rubin to General Availability

Platform support: Vera Rubin and DGX Station for Windows

According to NVIDIA, Vera Rubin support in CUDA 13.5 is now ready for enterprise production. Windows on Arm support, which has been generally available since CUDA 13.4, now also covers NVIDIA DGX Station for Windows.

The release also changes how Windows drivers work on the new hardware. Starting with the NVIDIA Rubin architecture, CUDA supports the Windows Driver Display Model (WDDM) and the Microsoft Compute Driver Model (MCDM), with MCDM serving as the compute-only model. Tesla Compute Cluster (TCC) is not supported on Rubin and later GPUs. NVIDIA advises that applications and deployment tools that assume TCC mode should use a supported WDDM or MCDM configuration for their target system.

More control over GPU scheduling

CUDA 13.5 gives applications a choice between uniform streaming multiprocessor (SM) partitions across locality domains and partitions that include all available SMs. By default, localized green-context partitions use the same guaranteed SM count per domain, which leaves supplemental SMs outside those partitions. A new flag, cudaDevSmResourceGroupLocalityDomainSupplementalSms, combined with cudaDevSmResourceGroupLocalityDomainId, includes those extra SMs in each selected domain. The resulting partitions may differ in size, and applications can use discovery mode in the cudaDevSmResourceSplit() API to get each partition's SM count and distribute work accordingly.

NVIDIA Multi-Process Service (MPS) v3 adds several controls over how workloads share a GPU:

• Weighted timeslicing: set a base timeslice, scale it per MPS server and tune how aggressively the GPU switches between workloads.
• SM partition load balancing: borrowing is enabled with --max-chunks, and a partition can lend its SMs while it has no attached clients with --shareable=true. MPS reclaims borrowed resources before reassigning them.
• Cgroup-based routing: a cgroup v2 subtree can be mapped to an MPS namespace, and clients connecting through the daemon's main socket are routed there automatically.
• Per-namespace SM partition assignments: a partition is chosen once per device and applied to every client in the namespace, so CUDA_MPS_SM_PARTITION no longer needs separate configuration for those clients.
• Polling-based memory accounting fallback: for cases where cgroup threshold notifications are missing or unreliable, MPS can read current usage and limits directly.

CUDA 13.5 also adds CUDA Graph support for batched 1D memory copies. Existing cudaMemcpyBatchAsync calls can be included in stream capture without changing the call syntax, and batched-copy nodes can be added explicitly.

CUDA Tile and CUDA Python

CUDA Tile kernels can now handle multi-GPU communication directly. Unicast pointers let a kernel access memory on another NVLink-connected GPU. Multicast pointers and dedicated multimem operations support reductions and stores across multiple GPUs on NVIDIA NVSwitch fabrics with NVIDIA NVLink SHARP support. NVIDIA says this enables workloads such as fused matrix multiplication and cross-GPU reduction.

A public preview of Tile to SIMT interoperability lets kernels written in cuTile Python or CUDA Tile C++ call device functions from SIMT libraries in the middle of their own code, on data already in registers or shared memory. Previously, Tile and SIMT library code could only be combined across kernel boundaries, with data passing through global memory. The libraries named are NVSHMEM, CCCL Coop, Warp and MathDx, and NVIDIA says each library will enable the interop support soon. In this release the preview covers library functions only. Calling a developer's own __device__ functions from tile code is planned for a future release.

To try it in C++, compile with nvcc --tile-preview simt and pass the tilelib to the tile compiler. In cuTile Python, use cuda.tile_preview.foreign_call from the cuda.tile_preview package.

On the Python side, the cuda.core 1.2 library introduces batched memory copies and Programmatic Dependent Launch (PDL), according to the post.

What it means for developers

For teams planning production deployments on Vera Rubin, the move to general availability removes the early-access label from the toolchain. Operators who share GPUs among many workloads gain finer control through MPS v3, while developers can decide between predictable, uniform SM partitions and using as much of the GPU as possible. NVIDIA directs developers to download CUDA Toolkit 13.5, the CUDA Runtime API documentation for locality domain details and the MPS v3 interface guide for configuration.